1. Field of the Invention
The present invention relates to fabricating of semiconductor features, and more particularly, to methods and apparatus for arranging mask patterns.
2. Description of the Related Art
One of the typical goals in integrated circuit fabrication is to faithfully reproduce an original circuit design on a semiconductor wafer using a mask while using as much area of the semiconductor wafer as possible. Another typical goal is to optimize exposure and improve image intensity on the semiconductor wafer. Yet another typical goal is to increase the depth of focus (DOF) and exposure latitude (EL). However, the microscopic size of mask features can make it difficult for light to pass through holes or lines in the mask. Consequently, the DOF and the EL that may be obtain using a mask can be reduced.
One conventional approach that attempts to overcome these difficulties includes using assist features that are arranged on a mask so that light intensity on a feature that is to be generated can be increased (which, in turn, can increase DOF and/or EL). Currently, such assist features are manually arranged by a semiconductor design engineer through a process of trial and error which is limited by the engineer's ability and skill, such that a large amount of time can be required and the assist features may not be arranged on a broad area of the mask relative to the overall pattern of the mask. Furthermore, if the mask has various different patterns thereon, it may be very difficult to generate the assist features in a stable manner. Therefore, a new approach is needed to allow rapid determination of the desired/optimal position of the assist features.